1. Field of the Invention
This invention relates generally to integrated circuit packaging, and more specifically to ball grid arrays. In particular, this invention relates to a chip scale ball grid array design employing a flex tape having a nonpolymer support structure.
2. Description of the Related Art
The demand for a reduction in size and an increase in sophistication of electronic components has driven the industry to produce smaller and more complex integrated circuits (ICs). These same trends have forced IC packages to have smaller footprints, higher lead counts and better electrical and thermal performance. At the same time, these IC packages are also required to meet accepted reliability standards.
With reduction in device sizes and corresponding increase in circuit complexity, integrated circuit packages are required to have smaller footprints, higher lead counts and higher electrical and thermal performance. At the same time, integrated circuit packages are also required to meet accepted reliability standards.
Ball grid array (BGA) packages were developed to meet the demand for integrated circuit packages having higher lead counts and smaller footprints. A BGA package is typically a square package with terminals, normally in the form of an array of solder balls, protruding from the bottom of the package. These terminals are designed to be mounted onto a plurality of bonding pads located on the surface of a printed circuit board (PCB) or other suitable substrate.
Recently, BGA packages have been fabricated using a tape automated bonding (TAB) process and flexible circuitry (sometimes referred to as TAB tape) which typically consists of copper traces on a thin polyimide substrate. Electrically conductive leads may be laminated on one or both sides of the TAB tape. This BGA design is commonly referred to as a Tape BGA (TBGA). In a TBGA design, the circuitry on the tape has leads which are connected to a semiconductor die through any of the conventional methods such as wire bonding, thermocompression bonding, or flip chips. If the circuitry is present on both sides of the tape, electrically conducting vias may extend through the tape from one layer of circuitry to another.
For some applications such as portable electronic components (cellular phones, disk drives, pagers, etc.), even BGA packages are sometimes too large. Consequently, solder bumps are sometimes deposited directly onto the surface of an IC itself and used for attachment to the PCB (commonly referred to as direct chip attach or flip chip). However, there are a number of problems associated with this approach. First, the deposition of solder balls requires a number of costly process steps. In addition, it is typically necessary to deposit a polymer underfill beneath a die to achieve acceptable reliability with flip chip attach to a PCB. This underfill is required to reduce thermal stress which is caused by the low thermal expansion of a die relative to the typically much higher expansion of a PCB ("thermal mismatch stress"). Deposition of this underfill is a costly process which eliminates the ability to rework the component. Consequently, if any defects are found, a valuable PCB must be thrown out.
To address concerns associated with flip chip processing, another class of BGA packages have been developed. This class of BGA package may be referred to as a chip scale ball grid array or a chip scale package (CSP). Chip scale packages are so called because the total package size is similar or not much larger than the size of the IC itself. In a chip scale package, solder ball terminals are typically disposed underneath a semiconductor die in order to reduce package size. One example of a CSP is a product developed by TESSERA called "MICRO BGA." This product consists of a flexible circuit with a soft compliant elastomer layer (or elastomer pad) between the die and the circuit. This elastomeric member consists of polymer materials such as silicone and is typically about 5-7 mils thick. One purpose of the elastomer is to obtain suitable reliability by minimizing thermal mismatch stress between the die and the PCB without the need for expensive underfill material.
Although current chip scale package designs offer improved board space utilization and ease of surface mount assembly, these products suffer from a number of shortcomings. First, it is often difficult to find a suitable elastomer material which meets industry requirements of low moisture absorption, low outgassing, and the ability to withstand cleaning solvents commonly used in the industry. For example, silicone is known to breakdown with some typically used cleaning solvents, and polymer materials in general tend to absorb and outgas moisture. If moisture absorption is too high, rapid outgassing of this moisture at reflow temperatures will cause voids to form at component interfaces and even bursting of the package. For example, moisture may release from polymer materials in a tape and become trapped within the die attachment adhesive.
Voids may then be formed when this trapped moisture expands during board assembly heating operations, typically causing cracking and package failure. Formation of such voids may be particularly acute during reflow attachment to a PCB.
Another significant challenge with chip scale package designs is the process for attaching the elastomer to the flex tape. One method commonly employed is to pick and place elastomer pads onto individual sites while another method involves screen printing is a fluid polymer followed by a cure. In either case, it is difficult to meet the tight tolerances required for a CSP application. Yet another concern is package flatness. In a typical CSP design, it is critical that the package flatness (coplanarity) be less than about 1 mil to ensure that all solder balls contact the PCB upon reflow. This level of flatness or coplanarity may be difficult to achieve with soft polymer and elastomer materials commonly used. Finally, if a die is not adequately isolated from other parts of a package, premature failure of solder ball joints may occur due to thermal stress generated between an assembled die and a substrate, such as a circuit board.
It is often desired to handle IC packages in strip format since a great deal of equipment currently exists for handling this configuration. For example, lead frames for quad flat packs have typically been processed in strips of four to eight units. Plastic BGA packages and some TBGA packages have also been produced in strip format for easy handling through the assembly process. Such strips are loaded into magazines which are used to feed assembly equipment for die attach, wire bonding, overmolding/encapsulating, solder ball attach, and other processing steps. Although some assemblers may desire to perform these processes in a reel to reel fashion, many may prefer the conventional strip format. However, conventional CSP designs employing elastomer pads lack sufficient rigidity for conventional strip format processing without some additional source of rigidity. For example, the TESSERA "MICRO BGA" design employs a metal frame adhered to the outer edge of a strip of parts to allow strip format processing. The use of such frames is not convenient and adds to the final cost of a product because it increases the complexity and number of components in a tape processing design, as well as requires additional steps to attach and remove the frames during processing. Therefore, although strip format processing has typically been used for integrated circuit packaging, no convenient strip format chip scale package design current exists.
In other CSP designs, elastomer pads have been directly laminated to circuitry and semiconductor dies without using layers of adhesive in an effort to eliminate void formation in adhesive layers. However, these designs still may suffer from thermal stress problems and do not possess sufficient rigidity for strip format processing.
In still other CSP designs, such as the TEXAS INSTRUMENTS "MICRO STAR BGA," an IC is adhered directly to the surface of a flex circuit without a polymer or elastomer pad. This structure does not decouple the die from the PCB, consequently, an expensive underfill material is required to achieve the required reliability in the solder joints. In addition, it has been found that moisture from polymer materials employed in this design outgasses during curing of the die attach adhesive, causing voids in the adhesive.
Consequently, a need exists for a low cost and solvent resistant chip scale package which has sufficient coplanarity, and which does not suffer from moisture and thermal stress related problems. A need also exists for a chip scale package which may be easily produced in strip format.